Hardware Support for Dynamic Type Checking

Principal Investigator: Luis Ceze

Dynamically typed languages have become a de-facto standard for web-based applications. Generating efficient code for dynamically typed languages, however, is a challenge because such languages require frequent dynamic type checks. An average of 12.9% of the instructions of a typical program relate to type checks. The overall efficiency of such a program could be greatly improved by improving the efficiency of type checking. Additionally, embedded processors do not typically employ the traditionally used heavy-weight architectural techniques for improving code execution efficiency. A light-weight architecture that can improve the execution efficiency of dynamically typed languages would be very useful for mobile computing devices.

The UW inventors have developed "CheckLoad," an architectural support for dynamic type checking as an alternative to software-based dynamic type checking. CheckLoad provides flexible and automatic type checks for memory operations, while requiring minimal hardware changes. They have demonstrated the benefits of this invention in the Nitro JavaScript compiler with up to 44.6% speedups on a mobile processor. 


• A computing device configured to execute dynamically typed programming languages. 

• A method of performing type checking during the execution of a program in a dynamically typed programming language. 

• A method for predicting a result of the comparison of the type tag.

• This invention improves the efficiency of type checking. 

• This system and method would increase efficiency of type checking for mobile computing devices. 

• This innovation provides a light-weight architecture for improving execution efficiency of dynamically typed languages.

For more info, contact: Laura Dorsey

  • swap_vertical_circlelibrary_booksReferences (1)
    1. Owen Anderson, Emily Fortuna, Luis Ceze, Susan Eggers (February 2011), Checked Load: Architectural support for JavaScript type-checking on mobile processors, Proc. of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture, 419 - 430
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